There exist applications in which there is a need to provide a variable-rate clock for timing recovery in direct-sequence spread spectrum (DSSS) communication systems. The present invention fulfills that need.
Various direct-sequence spread spectrum (DSSS) communication systems are known. For example, see U.S. Pat. No. 5,060,180 issued Oct. 22, 1991 for "Programmable Digital Loop Filter" by Samuel C. Kingston et al; U.S. Pat. No. 5,128,958 issued Jul. 7, 1992 for "Digital Time Error Signal Generator" by Samuel C. Kingston et al; and U.S. Pat. No. 5,099,494 issued Mar. 24, 1992 for "Six Channel Digital Demodulator" by Samuel C. Kingston et al, each of which are hereby incorporated by reference herein. Each of the three above-identified Kingston et al patents refers to or includes a clock error signal Es for controlling a clock synthesizer. Kingston et al '180 shows a clock synthesizer 77 in its FIG. 2. Kingston et al '958 shows a clock synthesizer 76 in its FIG. 2. Kingston et al '494 refers to a clock synthesizer at column 3, line 48.
In Kingston et al '180, a programmable second order loop filter is provided with first and second programmable scaling circuits arranged in parallel and having their outputs connected to first and second programmable one bit serial adders respectively. The output of the second programmable serial adder is coupled to the input of the first programmable serial adder and has its output coupled to the input of a programmable output stage so as to provide the ability to maintain the average quantization bit error to one-half of one bit of the least significant bit of the full loop filter width even though the output does not use or employ all of the significant bits. FIG. 2 of the Kingston et al '180 patent shows a phase-locked loop employing a clock synthesizer 77 and passing through receiver stages 10, demodulator 54, line 55, switch 67, line 76, clock synthesizer 77, line 78, master clock or system clock 72, line 73, timing and control circuit 74 and line 53 applied to the clock input of receiver stages 10.
In Kingston et al '958, a time error signal generator of the type employed in symbol time tracking loops is provided with a pre-accumulate and scale circuit for receiving an input data stream which is applied to a digital early sample-late sample circuit for generation of an error signal indicative of a time magnitude difference between the analog transition time of the data and the chip strobe time multiplied by the sign of the data. The output of the early sample-late sample circuit is applied to a second accumulate and scale circuit for generating an accumulated error signal which is applied to an inverter. The inverter is provided with a decision directed tracking input indicative of the sign of the data sample and is employed to invert the accumulated error signal when the sign of the analog data is negative. The output of the inverter provides a digital time error tracking signal which is adapted to be coupled to a clock generation circuit or clock synthesizer for generating the tracking loop system clock as well as other strobe timing signals. Kingston et al '958 shows a phase-locked loop passing through its second order filter 74 and clock synthesizer 76, the latter producing the system clock 53 applied to components 51, 29 and 42.
Kingston et al '494 describes a six channel programmable digital demodulator of the type designed to be manufactured as an integrated circuit with other components. This demodulator comprises a code channel, a level channel and a phase channel, each of which includes two accumulate and scale circuits. Each of the accumulate and scale circuits is connected to an I or a Q channel of the data which has been despread after being received from the communications receiver. The outputs of two of the accumulate and scale circuits are applied to a two to one multiplexor which is controlled by a command generator to provide a selectable output defining a clock error signal. The remaining four accumulate and scale circuits are connected to a first four to one multiplexor to provide a selectable output defining a clock error signal. The same four remaining outputs from the accumulate and scale circuits are connected to a second four to one multiplexor having an output defining a carrier error signal.